In modern electronic devices, it is often necessary to transfer data between circuits in different digital clock domains. Although in many cases the clocks in the different domains are entirely unrelated, occasionally the clocks are generated from a common base clock or otherwise have a frequency relationship that may be used to time the transfer of data. In such cases, it is often critical to accurately align the phases of the clocks to provide deterministic timing relationships for data transfer. Unfortunately, accurate phase alignment is difficult in high frequency systems, because even very small sources of timing offset tend to produce proportionally large phase errors.
FIG. 1 is a diagram of a prior art memory system 10 that includes phase alignment logic for maintaining phase alignment between a host clock 16 (HCLK) and a memory clock 17 (MEMCLK). A reference clock generator 12 generates a reference clock 15 and outputs the reference clock 15 to a memory controller 25 and to a memory clock generator 14. The memory clock generator 14 includes a frequency multiplier circuit 21 that multiplies the reference clock 15 to produce a raw memory clock 13. The raw memory clock 13 is forwarded to a phase adjusting circuit 22 which incrementally adjusts the phase of the raw memory clock 13 to produce the memory clock 17. The memory clock 17 is output from the memory clock generator 14 by an output buffer 23 and supplied to a memory array 19 and to the memory controller 25.
The memory controller 25 receives the reference clock 15 and uses it to generate the host clock 16. The memory controller 25 includes host-side control logic 27 which is clocked by the host clock 16 and memory-side control logic 29 which is clocked by the memory clock 17. The host-side control logic 27 responds to memory access requests received from external agents by issuing commands to the memory-side control logic 29 to read and write the memory array 19. The memory-side control logic 29 responds to the commands from the host-side control logic 27 by issuing read and write commands to the memory array 19 via memory interface 42. Data to be written to the memory array 19 is supplied by external agents and forwarded by the host-side control logic 27 to the memory-side control logic 29, which in turn transfers the data to the memory array. Data read from the memory array 19 is forwarded by the memory-side control logic 29 to the host-side control logic 27 which in turn transfers the data to a requesting agent. The memory-side control logic 29 also includes a buffer 40 and dividing circuit 41 for generating a divided version of the memory clock 43. Because the divided version of the memory clock 43 is further divided by other circuitry in the memory controller, clock signal 43 is referred to as a partially divided memory clock 43 (PD MEMCLK).
The memory controller 25 also includes gear ratio logic 31 which includes respective dividers 34 and 36 to divide the host clock 16 and the partially divided memory clock 43 into respective clock signals that have a common frequency, called a beat frequency. The divided host clock 46 (HCDIV) and the divided memory clock 47 (MCDIV) are supplied to the phase adjuster 22 in the memory clock generator 14. The phase adjuster 22 reacts to the divided clock signals 46, 47 by detecting which of the clock signals 46, 47 leads the other and incrementally advancing or retarding the phase of the memory clock 17 accordingly. Using the phase difference between the divided clock signals 46, 47 as feedback, the phase adjuster 22 ideally drives the phase difference between the host clock 16 and the memory clock 17 to zero.
As mentioned above, accurate clock phase alignment becomes difficult in high frequency systems, because even very small sources of timing offset tend to produce proportionally large phase errors. In the prior-art system of FIG. 1, for example, the memory clock generator 14 is typically implemented as a discrete integrated circuit (IC), rather than being integrated with the memory controller 25 on a single IC. Consequently, signal paths from the dividing circuits 34, 36 to the memory clock generator 14 are relatively long and output buffers 37, 38 are typically required to drive the divided clock signals 46, 47 off-chip to the memory clock generator 14. Routing delays in the signal paths from the dividers 34, 36 to the output buffers 37, 38 to the memory clock generator 14 usually must be closely matched, because any offset in these delays tends to produce a corresponding offset between the host clock 16 and the memory clock 17. This imposes significant constraints on the layout of the memory controller IC and on the board-level layout of the signal traces used to carry the divided clock signals 46, 47. Further, the output buffers 37, 38 typically require separate, quiet ground and power supplies to avoid introducing switching noise from adjacent interfaces. Otherwise, the divided clock signals 46, 47 supplied to the phase adjuster 22 may have jitter contributing to the uncertainty of the phase alignment between the memory clock 17 and the host clock 16. Unfortunately, providing a separate power and ground supply requires two additional pins on the memory controller IC, often a scarce and valuable resource. Thus, the need to provide closely matched routing delays and quiet power and ground add to the complexity and expense of memory controller and board-level design. On the other hand, timing offset in the divided clock signals 46, 47 due to lack of care in signal routing or insufficient noise suppression may result in unacceptably small timing margins in the interface between the host clock and memory clock domains.